/*Yipeng Huang and Scott Rogowski*/
/*yh2315 smr2167*/

module ALU (ALU_input_0, ALU_input_1, ALU_op, ALU_result, ALU_zero);

input [31:0] ALU_input_0;
input [31:0] ALU_input_1;
input [1:0] ALU_op;
output [31:0] ALU_result;
output ALU_zero;

wire comp_result;
wire [31:0] add_result;

reg ALU_zero_mid;
reg [31:0] ALU_result_mid;

Comparator comp (.comp_input_0(ALU_input_0), .comp_input_1(ALU_input_1), .comp_result(comp_result));
Adder add (.add_input_0(ALU_input_0), .add_input_1(ALU_input_1), .add_result(add_result));

always @(*) begin

	if (ALU_op[0]) begin
		ALU_zero_mid = comp_result;
		ALU_result_mid = 32'b0;
		end
		
	else if (!ALU_op[0]) begin
		ALU_zero_mid = 1'b0;	
		ALU_result_mid = add_result;
		end
		
	else begin //only if ALU_op is indeterminant
		ALU_zero_mid = 1'b0;
		ALU_result_mid = 32'b0;
		end
		
	end

assign ALU_zero = ALU_zero_mid;
assign ALU_result = ALU_result_mid;

endmodule